A Phase Locked Loop with Arbitrarily Wide Lock Range for Software Defined Radios

Phase locked loops (PLLs) are frequently used in Software Defined Radios (SDR) for carrier recovery and symbol timing synchronization. Unfortunately, conventional PLLs can function correctly only when the frequency offset remains within a relatively small and limited range. This limited lock range is a direct consequence of the inability of the phase detector to resolve any phase error that lies outside a given 2π range. In this paper, we propose an extended lock range PLL that benefits from the flexibilities offered when the design is implemented in software. We describe and examine the FPGA implementation of a tracking system that uses the extended range PLL to perform carrier recovery. The proposed system is applicable to both QAM and PSK signaling and shown to function at a relatively fast clock frequency using a very small percentage of the resources on a Xilinx Virtex-IV FPGA.